Applicant hereby incorporates by reference Japanese Application No. 2000-382395, filed Dec, 15, 2000, in its entirety.
The present invention includes semiconductor devices having a field effect transistor and a bi-polar transistor, and methods for manufacturing the same.
A MOS field effect transistor with an SOI structure can be driven at a low power consumption and at a higher speed compared to an ordinary MOS field effect transistor.
FIG. 20 schematically shows one example of a MOS field effect transistor with an SOI structure. An embedded oxide film 1100 that is formed from a silicon oxide film is formed on a silicon substrate 2000. A source region 1200 and a drain region 1300 are formed on the embedded oxide film 1100. A body region 1400 is formed on the embedded oxide film 1100 and between the source region 1200 and the drain region 1300. A gate electrode 1500 is formed on the body region 1400 through a gate dielectric layer.
It is noted that the body region 1400 of the MOS field effect transistor is in a floating state. Accordingly, carriers that are generated by an impact ionization phenomenon are stored in the body region 1400. When carriers are stored in the body region 1400, the potential of the body region 1400 changes. A phenomenon that is a so-called substrate floating effect takes place. When the substrate floating effect occurs, a kink phenomenon and a history effect occur in the MOS field effect transistor.
Embodiments include a semiconductor device. The device includes an insulation layer, a semiconductor layer formed on the insulation layer, an element isolation region formed in the semiconductor layer, element forming regions defined by the element isolation region; and a bi-polar transistor and a field effect transistor in at least one of the element forming regions; The device also includes a body region formed at least between a source region and a drain region. The body region is electrically connected to the source region. The body region is electrically connected to a base region. The drain region is electrically connected to a collector region, and the source region is structurally isolated from an emitter region.
Embodiments also include a semiconductor device including an insulation layer, a semiconductor layer formed on the insulation layer, an element isolation region formed in the semiconductor layer, element forming regions defined by the element isolation region, and a bi-polar transistor and a field effect transistor in at least one of the element forming regions. The bi-polar transistor includes an emitter region of a first conduction type, a base region of a second conduction type, and a collector region of the first conduction type. The field effect transistor includes a gate electrode layer, a source region of the first conduction type, and a drain region of the first conduction type. A first body region of the second conduction type is formed at least between the source region and the drain region, wherein the first body region of the second conduction type is electrically connected to the source region, the first body region of the second conduction type is electrically connected to the base region, the drain region is electrically connected to the collector region, and the source region is formed structurally isolated from the emitter region.
Embodiments also include a semiconductor device including an insulation layer and a semiconductor layer formed on the insulation layer. The device also includes an element isolation region formed in the semiconductor layer, element forming regions defined by the element isolation region, and a bi-polar transistor and a field effect transistor in at least one of the element forming regions. A gate electrode layer is formed on the semiconductor layer. The gate electrode layer is formed in a manner to cross over the element forming region, and a first electrode layer is formed on the semiconductor layer, wherein the first electrode layer has one end section continuing to a side section of the gate electrode layer, and another end section reaching the element isolation region,. A first impurity diffusion layer of a first conduction type is formed in at least a part of a first region surrounded by the gate electrode layer in the field effect transistor forming region, the first electrode layer and the element isolation region. A second impurity diffusion layer of the first conduction type is formed in a second region surrounded by the gate electrode layer and the element isolation region. A third impurity diffusion layer of the first conduction type is formed in a third region defined by the gate electrode layer in the bi-polar transistor forming region, the first electrode layer and the element isolation region. A first body region of a second conduction type is formed below the gate electrode layer in the field effect transistor forming region and the first electrode layer. A first impurity diffusion layer of the second conduction type is formed below the gate electrode layer in the bi-polar transistor forming region and the first electrode layer and along a periphery of the third impurity diffusion layer of the first conduction type. A first body region of the second conduction type is electrically connected to the first impurity diffusion layer of the first conduction type, and the first body region of the second conduction type is electrically connected to the first impurity diffusion layer of the second conduction type.
Embodiments also include a method for manufacturing a semiconductor device including an insulation layer and a semiconductor layer formed on the insulation layer, the method including the steps of: (A) forming an element isolation region in the semiconductor layer to define element forming regions; and (B) forming a field effect transistor and a bi-polar transistor in the same one of the element forming regions, wherein the step (B) comprises the steps of: (B-1) forming a first body region of a second conduction type in the semiconductor layer in a forming region where at least a part of a gate electrode layer is to be formed and in a forming region where a first electrode layer is to be formed; (B-2) forming the gate electrode layer and the first electrode layer on the semiconductor layer, wherein the first electrode layer continues to a side section of the gate electrode layer and reaches the element isolation region; (B-3) forming an impurity diffusion layer of the second conduction type in the semiconductor layer in a third region surrounded by the gate electrode layer in the bi-polar transistor forming region, the first electrode layer and the element isolation region; (B-4) conducting a thermal treatment to thermally diffuse the impurity diffusion layer of the second conduction type to form a base region of the bi-polar transistor below the gate electrode layer and in the semiconductor layer below the first electrode layer, and to electrically connect the base region and the first body region of the second conduction type, (B-5) forming a source region of a first conduction type of the field effect transistor at least in a part of a first region surrounded by the gate electrode layer of the field effect transistor, the first electrode layer and the element isolation region; (B-6) forming a drain region of the first conduction type of the field effect transistor in a part of a second region surrounded by the gate electrode layer and the element isolation region; (B-7) forming a collector region of the first conduction type of the bipolar transistor in a part of the second region; (B-8) forming an emitter region of the first conduction type of the bi-polar transistor in the third region; and (B-9) electrically connecting the first body region of the second conduction type and the source region.
Embodiments also include a method for manufacturing a semiconductor device including an insulation layer and a semiconductor layer formed on the insulation layer. The method includes the steps of: (A) forming an element isolation region in the semiconductor layer to define element forming regions; and (B) forming a field effect transistor and a bipolar transistor in the same one of the element forming regions, wherein the step (B) includes the steps of: (B-1) forming a first body region of a second conduction type at least in the semiconductor layer in a forming region where a gate electrode layer is to be formed and in a forming region where a first layer is to be formed; (B-2) forming a gate electrode layer on the semiconductor layer; (B-3) forming a first layer on the semiconductor layer, wherein the first layer has one end section that continues to the gate electrode layer or a second layer and another end section that reaches the element isolation region; (B-4) forming a second layer on the semiconductor layer, wherein the second layer has one end section that continues to the gate electrode layer or the first layer and another end section that reaches the element isolation region; (B-5) forming an impurity diffusion layer of the second conduction type in the semiconductor layer in a third region surrounded by the first layer, the second layer and the element isolation region; (B-6) conducting a thermal treatment to thermally diffuse the impurity diffusion layer of the second conduction type to form a base region of the bi-polar transistor below the first layer and in the semiconductor layer below the second layer, and to short-circuit the base region and the first body region of the second conduction type; (B-7) forming a source region of the first conduction type of the field effect transistor at least in a part of a first region surrounded by the gate electrode layer, the first layer and the element isolation region; (B-8) forming a drain region of the first conduction type of the field effect transistor in a part of a second region surrounded by the gate electrode layer, the second layer and the element isolation region; (B-9) forming a collector region of the first conduction type of the bi-polar transistor in a part of the second region surrounded by the gate electrode layer, the second layer and the element isolation region; (B-10) forming an emitter region of the first conduction type of the bi-polar transistor in a third region surrounded by the first layer, the second layer and the element isolation region; and (B-11) electrically connecting the first body region of the second conduction type and the source region.